|
Description:
|
|

- Luke just got back from Maker Faire Bay Area
- Arduino FPGA board
- Want lots of serial ports
- Porting sketches from one micro to another
- FPGAwars
- Remake of Pong
- Need tools for things to be simpler
- Tim Mithro Ansell
- Clifford Wolf who started project ICEstorm
- FPGAwars hashtag
- APio for building FPGAs
- Obijuan Academy
- Learning Verilog
- Data pipeline vs State machines and control
- Similar to an “if” statement on a micro
- Faster to write imperative code
- Serial port example
- Low power FPGA collects data, wakes up the micro and then transmits
- “You’re not writing code any more, you’re describing hardware”
- Wants to be able to take code and then sythesis in logic
- Why is FPGA needed in a world of cheap micros
- Amazing $1 microcontroller
- When should people switch to an FPGA
- Customized peripherals
- Being sure of the hardware that’s going into micr
- FGPAs have room for change in the future (Especially if you think the protocol will change in the future)
- 0h 29m 54s
- Chris has experienced this with a video recorder that sells digital upgrades.
- Also useful in test jigs to emulate hardware
- Explaining the hardware
- A series is 1.2×0.7
- Same size as Teensy
- Doesn’t have the end pins like the Teensy
- Buy the boards on Tindie
- Difference between a and b series
- Bugblat tif
- Learned surface mount soldering
- Can find purchaseable boards and more on TinyFPGA.com
- Lattice Mach XO2
- CPLD replacement
- No DSP blocks
- Might be able to fit a micro in A2
- A2 has a hard SPI block
- Put store up on tindie for A1
- Digilent clint cole
- Having a board on the shelf could help for projects/hackathons/when in a bind
- There used to be a B2
- USB connector is SMT
- BX board is 4 layer with BGA ICE40 81 ball 0.4 pitch
- Package is meant to be used in a high density interconnect
- B2 pins are mostly IO
- Leaves some pins tri-stated and breaks out the deep hard IP blocks
- Using PCBway with 4/4 process, via is 0.2 mm
- Wanted more IO for the Bx boards
- Squished pads narrower and elongated them
- Everything is on github
- Choose your side t-shirt
- Re-using pins like the SPI flash
- Once config is complete, the SPI is handed over to the user design
- Recommends moving to a larger package
- Decided not to do castellation
- B series guide
- BX has a different pin constraint file
- Recommends using APio on commandline
- IDE using Atom with APio plugin
- Using IceCube2 toolchain
- APio supports mostly pin constraints
- Symbiflow is the next gen of opensource tools
- FPGA_dave
- ECP5 will be the next FPGA
- Wants to use SERDES
- Targeting crowdfunding campaign in fall
- Currently have to preorder the BX, due in July
- B series has an USB in the FPGA fabric
- Gets enumerated as a serial port
- Users can pull in the USB device to their projects
- Can store metadata in the spi flash that talks to the programmer
- Like a map file + UID
- Dave Vandenbout XESS
- Professor in Egypt doing FPGA online compiler
- SDR radio people
- Hackaday Supercoference
- Ordered 1250 boards, 600 ordered
- TinyFPGA on Twitter, GitHub, Tindie. Luke is on Hackaday as lukevalenty
|